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HABER PAPER / NEWSROOM

Chips and semiconductors — Page 3

Semiconductor design, manufacturing, equipment and supply chains for chip raw materials. Page 3.

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Researchers move robot scene mapping to an FPGA edge platform

A preprint presents LENS, a system for camera localization and neural scene rendering on an AMD KR260 FPGA and ARM platform. The work adapts a scene-coordinate and Gaussian-splatting pipeline to an edge device, with the goal of operating without a desktop GPU.

Source: arXiv
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Small-scale C. elegans neural simulation on Loihi-2

A preprint describes a workflow for mapping a small neural simulation of Caenorhabditis elegans to Intel’s Loihi-2 neuromorphic hardware through NeuroML2Loihi. The study addresses the cost of repeatedly updating neural and synaptic states in software.

Source: arXiv
1 min read

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PACT: NVFP4 Data-Flow LoRA Fine-Tuning on Consumer GPUs

Researchers introduce PACT, a system for LoRA fine-tuning on consumer GPUs that uses native NVFP4 matrix operations for frozen projections. The paper also addresses memory spent on activations and the cost of quantizing and dequantizing data.

Source: arXiv
1 min read

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EdgeKernelBench: Unified LLM-Driven Kernel Generation for Edge Backends

EdgeKernelBench studies whether large language models can generate kernels for varied edge-computing hardware. The preprint introduces a common intermediate representation and a hierarchical benchmark that connects workloads to different backends.

Source: arXiv
1 min read

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Koi proposes self-calibrating planning for multi-cloud LLM inference

A preprint introduces Koi, a cluster planner for large language model inference across heterogeneous multi-cloud fleets. It considers accelerator choice, parallelization, serving engines, replica counts and changing workloads as interdependent operating decisions.

Source: arXiv
1 min read

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Muse Glimmer 30B: An On-Device Agentic Model

A research preprint introduces Muse Glimmer, an open-source 30-billion-parameter causal language model with a perception encoder for agent tasks on consumer hardware. The authors describe text and image input, multi-step reasoning, tool use and failure recovery.

Source: arXiv
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First-Order LoRA Training with Phone NPUs

The preprint examines whether smartphone neural processing units can help fine-tune language models locally with low-rank adaptation. It focuses on the repeated operations involving frozen model weights that remain costly even when only a small number of parameters are trained.

Source: arXiv
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SpikeDuet studies sparse neural networks on microcontroller accelerators

The authors examine whether the matrix-vector processor inside a commodity EFR32MG24 microcontroller can accelerate sparse spiking-neural-network inference beyond an optimized Cortex-M33 CPU. Their toolchain maps snnTorch models to C and reorders neurons to improve accelerator use.

Source: arXiv
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UNT team moves thermal-imaging materials research into a second phase

The University of North Texas says its new project phase will test candidate materials for infrared sensors and examine whether they can be made with existing semiconductor processes.

Source: University of North Texas College of Science
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TiAs single crystals show distinctive band and transport features

An October 9 preprint coauthored by a University of Maryland researcher examines the topology and angular magnetoresistance of hexagonal TiAs crystals grown by chemical vapor transport.

Source: arXiv preprint 2610.12925
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Theory predicts phonon frequency combs in twisted 2D materials

An October 9 preprint from BITS Pilani Dubai uses first-principles calculations to predict phononic frequency combs in two twisted transition-metal dichalcogenide heterostructures.

Source: arXiv preprint 2610.13825
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A UV fluorescence chip design combines AlGaN and silicon

An October 9 preprint from a University of Massachusetts Boston researcher describes a sensor layout integrating a laser, photodiode and readout electronics on sapphire.

Source: arXiv preprint 2610.13525
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