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Türkçe sürüme geçSemiconductor design, manufacturing, equipment and supply chains for chip raw materials.
52 stories
BusinessEvent / data period:
At the BUILD 2026 conference, the communications minister cited power, connectivity, cloud access and advanced chips as constraints on local AI growth.
EconomyEvent / data period:
The province’s exports declined 0.9% and imports 5.7% month over month in August; exports were down 2.7% year over year for the first eight months while imports rose 1.3%.
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Researchers from Ottawa, Columbia and Hanyang reviewed post-CMOS materials and device approaches for artificial neurons; the work is a literature review, not a new chip prototype.
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The Canadian AI-chip company says it will use the new funding to scale Galaxy servers and advance processor technology it licenses to customers.
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Micron announced strategic funding to help Indium Corporation expand refining and manufacturing in Rome, New York, including a restart of domestic critical-minerals processing for advanced semiconductor manufacturing.
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NTT, NTT Innovative Devices, Japan Semiconductor, Furukawa Electric and Shinko Electric said a proposal led by NTT Innovative Devices was selected for a Japanese NEDO advanced-semiconductor programme. The project will develop manufacturing, testing and packaging methods for optical chiplets used to connect processors with light.
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Japan’s NEDO selected Preferred Networks and Tenstorrent for a joint xPU design project incorporating photonics-electronics integration. Their five-year research programme targets processor systems for training and inference across scientific, physical and agentic AI workloads.
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The sponsored-research agreement funds a one-year fabrication and testing programme for straintronic magnetic tunnel junction devices, which the parties say could inform energy-efficient AI hardware.
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Socionext says it is extending agentic AI from front-end design tasks into physical design for a large-scale 3nm system-on-chip, using Cadence InnoStack AI Super Agent.
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A preprint describes an analog memory architecture that stores multiple high-dimensional vectors in superposed form, aiming to reduce the number of memory cells needed for neural-network weights and embeddings. The authors say they demonstrate vector storage and retrieval.
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Brookhaven, Princeton Plasma Physics Laboratory, DIII-D and Great Sky demonstrated a superconducting neural-network chip on plasma-control tasks. Two tasks used DIII-D data sampled at one million points per second; another used simulated data.
BusinessEvent / data period:
A preprint presents CEMA-Router, an infrastructure-aware method for routing batches of language-model inference requests across cloud and edge resources. The design considers differences in compute capacity, energy efficiency, network conditions and model quality.
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