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Chips and semiconductors — Page 2

Semiconductor design, manufacturing, equipment and supply chains for chip raw materials. Page 2.

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Researchers propose a type system for communication-safe hardware design

The paper introduces a type system for describing clock-sensitive communication protocols between hardware components. It aims to identify mismatches that can lead to unsynchronized exchanges or stalled progress when separately designed components are combined.

Source: arXiv
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UnO-NeSy: FeFET In-Memory System for Neuro-Symbolic Computing

Researchers propose UnO-NeSy, a unified ferroelectric field-effect transistor in-memory architecture for neuro-symbolic AI. The paper targets the memory demands of combining neural perception with symbolic reasoning and hyperdimensional computing.

Source: arXiv
1 min read

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Preprint proposes shared-memory architecture for language-model serving

The paper studies a hybrid architecture that pairs GPUs with processing-near-memory resources and shared DRAM for large language model inference. It focuses on prefill and decode phases, which stress compute and memory bandwidth differently when serving requests.

Source: arXiv
1 min read

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Researchers model radiation-induced memory errors with generative AI

A preprint describes an error model based on read/write tests from a low-power ferroelectric RAM chip carried on a CubeSat in low Earth orbit. The authors say observed bit errors often formed regular spatial patterns, which their generative method learned.

Source: arXiv
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SIXPPAC: mixed-signal streaming machine-learning engine for wireless baseband

A preprint presents SIXPPAC, a mixed-signal machine-learning engine for real-time integrated sensing and communication in wireless baseband. Its design combines two successive-approximation ADCs with a six-layer digital binary-weight neural network.

Source: arXiv
1 min read

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Tandem: Serving GUI Agents on Mobile NPUs

The preprint studies local serving of smartphone graphical-interface agents using hybrid linear-attention models on mobile neural processing units. Such agents repeatedly inspect a screen and choose an action, so inference delay can accumulate across steps.

Source: arXiv
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Study maps quantization trade-offs for language models on edge NPUs

A preprint examines combinations of shared scales, weights and activations in MX-like low-precision formats for large language model inference. The researchers jointly explore model accuracy and estimated silicon trade-offs when integrating a tensor core with an edge neural processing unit.

Source: arXiv
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Preprint reports terabit-scale optical transmitter for AI data movement

The authors describe an optical transmitter built around thin-film lithium tantalate, aimed at moving data between computing chips with less reliance on power-hungry electrical links. The design combines multiple wavelengths to raise channel capacity while limiting the number of lasers and fibres.

Source: arXiv
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Learn the Interface, Not the Implementation: LLM-Based RTL Generation

The authors compare how output representation affects language-model generation of register-transfer-level hardware code. Their bounded task is generating SECDED error-correcting memory wrappers under formally checkable correctness conditions.

Source: arXiv
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SpecKCast proposes spectral forecasting to reduce diffusion-model inference

A preprint introduces SpecKCast, a feature-forecasting method intended to reduce repeated transformer evaluations in diffusion models. It uses a spectral Kalman approach to predict features at skipped denoising steps, extending work on caching intermediate features.

Source: arXiv
1 min read

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Resolving the Thermal Labyrinth inside 3D-IC Stacks

Researchers present a method for three-dimensional thermal characterization of advanced 3D integrated circuits. The workflow extracts thermal properties by layer and builds a location-specific database to examine how heat moves through a stack.

Source: arXiv
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