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Researchers present a method for three-dimensional thermal characterization of advanced 3D integrated circuits. The workflow extracts thermal properties by layer and builds a location-specific database to examine how heat moves through a stack.

They demonstrate the method on a sample with 2.2-micrometre through-silicon vias and about 2-micrometre-pitch face-to-face hybrid bonding. The preprint describes measurement research relevant to chip thermal management, not a production-ready cooling system.